1. Field of the Invention
The present invention relates generally to automatic bit fail mapping for embedded memories with clock multipliers, and more particularly pertains to automatic bit fail mapping for embedded DRAMs (Dynamic Random Access Memories) with clock multipliers.
More specifically, a system and method are provided of automatic bit fail mapping of embedded memories such as DRAM arrays on a chip while using a low-speed, off-chip ATE (Automatic Test Equipment) tester. BIST (Built In Self Test) test circuitry on the chip is run from an internal high-speed clock that is a multiplied frequency of the low-speed ATE tester clock. An accurate bit fail map of an embedded DRAM memory is provided by stopping the BIST test circuitry at a point when a fail is encountered, namely a mismatch between BIST expected data and the actual data read from the array, and then shifting the bit fail data off the chip using the low-speed ATE tester clock. Thereafter, the high-speed test is resumed by again running the BIST using the high-speed internal clock, to provide at-speed bit Fail Maps.
As embedded memory sizes continue to increase, overall BIST (Built In Self Test) testing time will also increase; hence, novel schemes that reduce test time while maintaining test integrity and diagnostic resolution are of great value. One current issue is that the ATE (Automated Test Equipment) tester, and specifically the ATE tester clock, is not fast enough to accommodate BIST testing. This can be addressed by having the BIST run off an internal clock that is a multiplied frequency of the ATE tester clock. However, the ability to accurately bit fail map a memory that is tested by an internal multiplied clock is inhibited by the inability to stop the test circuitry at the exact point when a fail is encountered, shift out the fail data, and then resume the test successfully.
2. Discussion of the Prior Art
ASIC (Application Specific Integrated Circuit) designs and SoC (System on a Chip) designs are being produced with ever increasing amounts of embedded DRAM memory. Tighter geometries have a greater effect on memory defect concentrations than in the surrounding logic. Decreasing process geometries increase the susceptibility to delay faults of all circuits, increasing the importance of at-speed testing. Automated Test Equipment (ATE) that can keep pace with on-chip clock speeds is becoming prohibitively expensive, rendering the capital investment necessary to provide at-speed test results undesirable.
The use of Built-In Self-Test (BIST) helps to alleviate the capital cost of high performance ATE, however at the expense of silicon overhead. Until recently, using BIST still implied that the clock speed of the BIST on the chip equated to the clock speed provided by the ATE tester. On chip clock frequency multiplication (PLL's, DLL's, etc.) enables at-speed BIST testing with a low cost, low-speed tester. On-chip memories can thus be tested at-speed with a low-speed ATE tester.
Generating pass/fail results using BIST with a multiplied clock is relatively straightforward, as is using a Built-In Redundancy Analyzer (BIRA) because the redundancy information never needs to come off the chip. Extracting the array Fail Map information off the chip requires that the tester be in sync with the memory under test. Up to now, generating a Fail Map with a low-speed ATE tester required low-speed BIST execution, because frequency domain changes between the ATE tester and the BIST test circuitry on the chip do not allow proper data collection.
Fail Maps are an essential tool to understand defects and improve yield. Thus, the capability to generate Fail Maps of embedded memory arrays is essential to the success of an embedded memory program, especially as increasingly more memory is being placed on a chip.
The capability to provide a Fail Map via BIST is much different than the traditional method of interfacing directly with the memory pins. On many SoC designs, the ATE tester often has no direct access to the memory and thus must rely solely on BIST for pass/fail results and any other, more detailed, diagnostics. Providing a means to identify all failing elements is necessary. Built-In Redundancy Analysis (BIRA) identifies which elements are failing and determines the optimal redundancy solution for memories with redundancy. The logic that supports BIRA can also be used to provide Fail Map data with minimal additional silicon cost.
Generating a Fail Map typically requires the BIST to run to a fail, at which point the tester suspends the test on the fail. The Fail Map data is then shifted out to the tester in “data slices” and the Fail Map slices are assembled and recreated in software. This method is acceptable for detecting stuck-at faults, the most common type of fault, and also works well for detecting speed related faults or delay faults, if the tester is capable of providing accurate clocks at a high enough frequency. As increases in on-chip clock frequency outpace the increases in ATE clock frequency, the capability to Fail Map an array at-speed becomes more difficult without large capital expenditures